The NEO comes with integrated 100 Mbps Ethernet while NEO Air provides network with 802. Both boards have a SD card slot, but NEO Air also includes 8GB eMMC. A binary option no loss air of functionality is provided via the unpopulated headers on both boards. 3mm mounting holes in the corners.
Allwinner H3 and single DDR3 chip mounted on the bottom. Sticker indicating amount of RAM is placed on the Ethernet jack. The H3 SoC support has matured since its introduction in kernel 4. For a more comprehensive list of supported features, see the status matrix for mainline kernels. See the Manual build section for more details. It boots a new variant of Allwinner’s 3.
39 BSP kernel, USB and Ethernet are working fine. Armbian images for NEO based on 3. FriendlyARM provides a BSP based on a newer Allwinner 3. You can build things for yourself by following our Manual build howto and by choosing from the configurations available below. The U-Boot repository and toolchain is described in the Mainline U-Boot howto. FEL using the OTG USB port. 4 kernel from the official Allwinner’s git repository does not support H3 yet.
Configure this kernel using sun8i_h3_defconfig, the rest is explained in the kernel compilation guide. 4 kernel with the mainline U-Boot, add the following line to boot. A newer H3 BSP variant appeared with tons of fixes which has been made available by FriendlyARM. A cleaned up fork has been adopted by Armbian project. On top of that Armbian maintains a bunch of 3. The mainline kernel has good support for the H3 SoC.
Please refer to the status matrix for a more detailed list of the development process, links to patches and links to kernel fork repositories. Air’s pin-out for those headers and the DVP camera connector can be found here. 0 analog audio signals were present on the 12-pin header that were replaced by digital audio starting with PCB rev. A red LED, labelled “PWR”, connected to the PL10 pin and to 3. GPIO is set to output low. A blue LED, labelled “STAT”, connected to the PA10 pin. Unlike the Xunlong boards which contain a thick copper layer inside the PCB to spread heat away from the SoC FriendlyARM chose a different design.
0 U7 next to DRAM is an LDO voltage regulator that provides 1. 2V for various SoC parts and 1. 1V for the internal Ethernet PHY. It overheats a lot and is rated 500mA max. DRAM is clocked at 432 MHz by the hardware vendor. The single bank DRAM configuration is slower than dual bank configuration on all other H3 devices.
Even more when taking the different DRAM clockspeeds into account. The one USB host port exposed as type A receptacle is usb3. Both usb1 and usb2 are available via solder holes. Four-pin UART0 header is placed next to USB type-A connector. For more instructions refer to our UART Howto. In the NEO Core variant, the ethernet and USB A connectors are replaced with unpopulated headers.